600 °C Logic Gates Using Silicon Carbide JFET's

NASA/TM--2000-209928

600 °C Logic Gates Using Silicon

Carbide JFET's

Philip G. Neudeck and Glenn M. Beheim

Glenn Research Center, Cleveland, Ohio

Carl S. Salupo

Cortez III Service Corporation, Cleveland, Ohio

=- T

March 2000

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NASA / TM--2000-209928

600 °C Logic Gates Using Silicon

Carbide JFET's

Philip G. Neudeck and Glenn M. Beheim

Glenn Research Center, Cleveland, Ohio

Carl S. Salupo

Cortez III Service Corporation, Cleveland, Ohio

Prepared for the

Government Microcircuit Applications Conference

cosponsored by DoD, NASA, DoC, DoE, NSA, and CIA

Anaheim, California, March 20-24, 2000

National Aeronautics and

Space Administration

Glenn Research Center

March 2000

Acknowledgments

The authors would like to gratefully acknowledge the tireless efforts of David Larkin, Luann Keys, and

Andrew Trunek in wafer preparation and epitaxial growth that made this work possible. This work

was carried out at NASA Glenn under internal funding from the High Temperature Enabling

Materials for Propulsion (HITEMP) program.

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600 °C Logic Gates Using Silicon Carbide JFET's

Philip G. Neudeck* and Glenn M. Beheim

National Aeronautics and Space Administration

Glenn Research Center

Cleveland, Ohio 44135

*Phone: (216) 433-8902, E-mail: [email protected]

Carl S. Salupo

Cortez III Service Corporation

Cleveland, Ohio 44135

Introduction

Complex electronics and sensors are

increasingly being relied on to enhance the

capabilities and efficiency of modern jet aircraft.

Some of these electronics and sensors monitor and

control vital engine components and aerosurfaces

that operate at high temperatures above 300 °C.

However, since today's silicon-based electronics

technology cannot function at such high

temperatures, these electronics must reside in

environmentally controlled areas. This necessitates

either the use of long wire runs between sheltered

electronics and hot-area sensors and controls, or

the fuel cooling of electronics and sensors located in

high-temperature areas. Both of these tow-

temperature-electronics approaches suffer from

serious drawbacks in terms of increased weight,

decreased fuel efficiency, and reduction of aircraft

reliability. A family of high-temperature electronics

and sensors that could function in hot areas would

enable substantial aircraft performance gains.

Especially since, in the future, some turbine-engine

electronics may need to function at temperatures as

high as 600 °C.

This paper reports the fabricalJon and

demonstration of the first semiconductor digital logic

gates ever to function at 600 °C. Key obstacles

blocking the realizaUon of useful 600 °Ctu_ine engine

integrated sensor and control electronics are outlined.

Technology Selection

Silicon carbide (SIC) presently appears to be the

strongest candidate semiconductor for

implementing 500-600 °C integrated electronics in

the nearer term, as competing high temperature

electronics technologies are either physically

incapable of functioning at this high of a

temperature range (silicon and silicon-on-insulator),

or are significantly less-developed (GaN, diamond,

etc.) than silicon carbide. Discrete silicon carbide

devices such as pn junction diodes, junction field

effect transistors (JFET's), and metal-oxide-

semiconductor field effect transistors (MOSFET's)

have previously demonstrated excellent electrical

functionality at 600 °C for relatively short time

periods [1]. However, for such electronics to be

useful in crucial turbine-engine applications, much

longer 600 °C harsh-environment lifetimes must

eventually be realized. Between 500 to 5000 hours

of operation is needed for various jet engine ground

tests, while many years of reliable operation is

required for insertion into everyday passenger

aircraft.

The operational lifetime of SiC-based transistors

at 600 °C is not limited by the semiconductor itself,

but is instead largely governed by the reliability and

stability of various interfaces with the SiC crystal

surface. The physical degradation of the metal-

semiconductor ohmic contact interface limits the

600 °C operating lifetime of all devices, while high

temperature MOSFET operating lifetime is also

limited by the electrical integrity of the oxide-

semiconductor. While silicon electronics experience

clearly demonstrates that complementary MOSFET

(CMOS) technology is desired for implementing

integrated circuits, development of the necessary

high electrical quality gate-insulators capable of

long-term 600 °C operation will likely prove elusive

for many years to come [2]. Thus, junction-based

transistors without gate insulators appear more

feasible in the nearer term, especially given recent

progress toward improving the 600 °C high

temperature durability of SiC ohmic contacts [3]. Of

the candidate junction-based transistor technologies

that might be used to implement SiC integrated

circuits, the pn junction gate JFET seems closest to

demonstrating long-term operation at 600 °C.

Prototype SiC bipolar transistors demonstrated to

date have exhibited low current gains insufficient for

practical use in complex integrated circuits, while the

Schottky barrier gates employed in SiC metal-

semiconductor field effect transistors (MESFET's)

allow too much undesired gate-to-channel leakage

at 600 °C [4].

NASA/TMn2000-209928 1

The basic current-voltageproperties of SiC

JFET's at 600 °C are qualitatively similar to room

temperature GaAs MESFET's employed in high-

speed digital IC's. Therefore, a resistive load direct-

coupled FET logic (DCFL) approach, with some

obvious parallels to high-yield GaAs DCFL, was

adopted to demonstrate simple 600 °C digital logic

using SiC JFET's. A simple inverter logic gate merely

requires a near-zero threshold voltage FET coupled

to a resistor.

The non-planar epitaxial gate JFET design

shown in Figure 1 was adopted in favor of a planar

ion-implanted structure, largely to alleviate the

challenging process of sufficiently activating high-

dose p+ ion implants in SiC. The two-level

interconnect approach uses oxidation-resistant

silicon nitride as the dielectric passivant along with

oxidation resistant gold for the metal interconnect.

Contrary to the depiction of Figure 1, the devices

are laid out so that both the second and third layers

of silicon nitride always covered the first via layer to

the oxygen-sensitive metal-SiC ohmic contact

interface. However, because non-optimized ohmic

contact metals were employed in this experiment,

long term 600 °C operation was not obtained.

Fabrication Process

The mesa-isolated epitaxial channel JFET

structure shown in Figure 1 was grown (starting from

an off-axis commercial p-type 6H-SiC substrate [5])

at the NASA Glenn Research Center using the

epitaxial growth system described in [6]. Proper

application of site-competition dopant control

principles was key to successfully realizing this

device structure [7]. An underlying p- buffer epilayer

around 12 microns thick and doped p-type below

5x1015 cm-3 is not depicted in Figure 1. A 0.5-0.7

_m n-channel layer doped around lx1016 cm-'3 was

grown to obtain threshold voltages acceptably close

to zero over the temperature range of interest. The

thin p* gate epilayer (0.1-0.2 #m, NA > 102o cm -3)

must be as degenerately doped as possible, to

assure sufficient electrical contact to the gate layer

as well as adequate conductivity through long

narrow gate fingers with no metal directly on top.

Site-competition enables all the key n-type and p-

type layers to be grown within a single continuous

run that minimizes undesired contamination and

dopant spikes that can arise from growth

interruption and re-initiation [8]. It also enables

better immunity to epi-reactor impurities that can

harm reproducibility as the reactor components,

especially the sample-holding susceptor, can

degrade from one growth run to the next.

Following epitaxlal growth, an aluminum p+ gate

pattern etch mask is defined and patterned by liftoff.

I Met2_

_//_Met!|! , I iMet! r.l-_

P Substrate

Figure 1: Simplified (see text) cross-sectional

representation of 6H-SiC epitaxiat JFET's used

to implement 600 °C logic gates. The shaded

regions are insulating silicon nitride dielectric.

A reactive ion etch (RIE) in 14 CHF3 : 10 02 400 W

plasma removes the p+ epilayer from unmasked

areas to expose the n-channel layer. Without

removing the first gate etch mask, a second

aluminum etch mask defining mesas for the active

n-channel areas is deposited and liftoff patterned. A

second RIE to a depth of approximately 0.7 p.m is

then carried out to isolate each device. Both

aluminum etch masks are then stripped with a wet

etch.

In preparation for ion implantation,

approximately 0.1 #m of silicon is E-beam deposited

over the entire wafer. Then, a 0.8 I_m layer of silicon

is liftoff patterned to delineate areas for high dose

nitrogen source/drain implants to facilitate ohmic

contacts to the n-channel layer. The wafers are then

sent to a commercial vendor [9] for 600 °C nitrogen

implantation of a box profile using 1.4x10_% 7x10 TM,

and 3.6x10 TM cm-2 doses at 80, 40, and 20 keV

energies, respectively. Following Ion implantation

the silicon mask layers are chemically stripped in 1

HF : 1 HNO3. The same basic implant process is

then repeated to carry out lighter-dose nitrogen

implant (3.2x10 _2,8x10 _, 1.2x10 _2,and lx1012 cm -2

dose at 33, 24, 18, and 10 keV, respectively) that

self-aligns with the etched p* gate as shown in

Figure 1. This second implant prevents complete

pinchoff of the n-layer resistors by the sub-channel

and surface depletion regions and increases

transistor source-to-gate and gate-to-drain

conductance. After implant mask stripping and

solvent/acid wafer cleaning, the nitrogen implants

are electrically activated by placing the wafer into a

closed SiC crucible (made from SiC wafer pieces)

and annealing at 1400 °C for 30 minutes in an

argon atmosphere tube furnace. The wafer is again

cleaned with acids to remove any residual oxides

that might have formed during the implant anneal.

NASA/TM--2000-209928 2

Figure 2: Optical micrograph of 6H-SiC JFET

NAND gate prior to 600 °C testing. The logical

output is the bottom left bondpad, while the

input pads are along the right side. The

positive (VDD)and negative (Vss)power supply

pads are on the top left and top middle,

respectively. Each bondpad is 100x100 p.m,

and each of the four gate fingers is 3x150 p.m.

A 0.3 p.m thick layer of gold (E-beam deposited,

patterned by liftoff) formed the contacts to both the

n÷ source/drain implant regions as well as the p+

gates. At this stage of the process, the basic

electrical functionality of the JFET's and resistors

was verified at room temperature on a probing

station.

A first layer of silicon nitride passivation was

sputter deposited to a thickness of around 0.3-0.4

p.m. The deposition of this layer was broken into two

segments to minimize chances of undesired pinhole

defects spanning the complete thickness of the

layer. Patterned vias through the first nitride layer

was then dry etched in a 5 CHF3 : 0.4 02 150 W

plasma using photoresist as the etch mask. 0.3 p.m

thick gold interconnects were then liftoff patterned

on top of the nitride. The same basic

nitride/via/metal process was then repeated for a

second level of gold interconnect. A third and final

nitride deposition and bondbad via etch completed

the circuit fabrication process. The completed NAND

and NOR gates are shown in the optical

micrographs of Figures 2 and 3.

Electrical Testino

All circuit testing was carried out in air under low-

light conditions using a probing station with the

sample sitting on a customized temperature-

controlled heating element. Gold-coated tungsten

probe tips were employed to minimize probe

degradation by oxidation during high temperature

testing.

Figures 4 and 5 show the functional waveforms

collected from the NAND and NOR gates at 300 °C,

respectively. Figures 6 and 7 show operation of the

Figure 3: Optical micrograph of 6H-SiC JFET

NOR gate following 600 °C electrical testing.

The bottom left bondpad is the output, while

the input pads are along the right side. The

positive (VDo) and negative (Vss) power supply

pads are on the top left and middle. Each

bondpad is 100×100 t_m, and each of the four

gate fingers is 3x150 p.m.

same gates at 600 °C. As indicated by the supply

voltages given in each figure caption, adjustment of

the substrate bias (Vsu_st,ate)and power supply bias

(VDD) was necessary to compensate for current-

voltage property changes with temperature, as the

circuit noise margins were not sufficient to absorb

these changes while maintaining basic functionality.

Therefore, these circuits are not capable of

operation over the desired 25 °C to 600 °C

temperature range using fixed power supply

voltages. High temperature degradation of both the

probe-tips and the ohmic contacts limited

operational circuit testing at 600 °C to less than one

hour. The Figure 3 device picture taken following

600 °C testing shows visible evidence of contact

degradation compared to the Figure 2 device photo

taken prior to high temperature testing.

Discussion

While the work described here does represent a

first for high temperature integrated circuit operation,

it also illustrates areas where additional technology

development is necessary before 600 °C SiC-based

circuits can become useful. The operational lifetime

of the circuit at 600 °C could be extended by using

separately optimized n-type and p-type ohmic

contacts specifically designed to resist high-

temperature degradation. However, it will be difficult

to measure this improvement on a probing station

where the probe tips themselves are degrading.

Therefore, the parallel development of 500-600 °C

packaging is very important to further development

of the chip-level technology. The ability to thermally

cycle packaged devices under electrical bias would

also aid the observation of longer term electrical

NASA/TM--2000-209928 3

1.0V

InputA

0V I

,_"! '__!_. r:_i_i _

Output :::::::i: :::::::i:::::i::::::::(:::::-

0 2 4 6 8

Time(msec)

Figure4" NANDgatetestwaveformsat 300°C

withVDD= 2.1V,Vss=0 V,Vsobst,ate= 0 V.

1.0V_

,n utA !

1.0V_

Input B

.......

Output

0 2 4 6 8

Time (msec)

Figure 5: NOR gate test waveforms at 300 °C

with VDD= 3.5 V, Vss = 0 V, Vsubstrat e _. 0 V.

1.0V

Input A

: : ; ,, :

OV ' : : ' '

......i........i................i.......i.......i................................

1.0 V ......_........_................_......._......._...............................

Input B0V _

1.ov=======================

Output t-- | i|--_ .......i-- | .......i-| .......i......

0 2 4 6 8

Time (msec)

Figure 6" NAND gate test waveforms at 600 °C

with VDD= 2.5 V, Vss = 0 V, Vsub,t,at_= -1.4 V.

1.0V_

Input A

1.0V

Input B

0V _ _ i

...... ! ........................ !................ !...............................

1.0 V ......_........................•................_..............................

Outpu. t

A+B

0 2 4 6 8

Time (msec)

Figure 7: NOR gate test waveforms at 600 °C

with VDD= 3.5 V, Vss = 0 V, V,ub_t,at_= -1.8 V.

instabilities like those shown to limit the operating

lifetime and usefulness of 300 °C operational

amplifier circuits based on SiC doped-channel

MOSFET's [10]. Effective elimination of such

instabilities, if present in integrated circuit compatible

SiC JFET's, will be necessary before 500-600 °C

integrated circuits implemented in this technology

can become useful.

References

[1]P.G. Neudeck, to appear in VLSI Technology,

CRC Press (2000).

[2]M. Maranowski and J.A. Cooper, IEEE Trans.

Electron Devices 46 p. 520 (1999).

[3] R.S. Okojie et al., IEEE Trans. Electron Devices

46 p. 269 (1999).

[4]J.W. Palmour et al., Physica B 185 p. 461

(1993).

[5] Cree Research, Durham, NC.

[6]J.A. Powell et al., J. Electronic Materials 24

p. 295 (1995).

[7]D.J. Larkin, Phys. Stat. Sol. (b)202, p. 305

(1997).

[8]A.A. Burk, Jr. and L.B. Rowland, Appl. Phys.

Lett. 68 p. 382 (1996).

[9] Implant Sciences Corporation, Wakefield, MA.

[10] D.M. Brown et al., Phys. Stat. Sol. (a) 162

p. 459 (1997).

NASA/TM_2000-209928 4

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March 2000 Technical Memorandum

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4. TITLE AND SUBTITLE

600 °C Logic Gates Using Silicon Carbide JFET's

6. AUTHOR(S)

Philip G. Neudeck, Glenn M. Beheim, and Carl S. Salupo

PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES)

National Aeronautics and Space Administration

John H. Glenn Research Center at Lewis Field

Cleveland, Ohio 44135-3191

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NASA TM--2000-209928

11. SUPPLEMENTARY NOTES

Prepared for the Government Microcircuit Applications Conference cosponsored by DoD, NASA, DoC, DoE, NSA,

and CIA, Anaheim, California, March 20-24, 2000. Philip G. Neudeck and Glenn M. Beheim, NASA Glenn Research

Center; and Carl S. Salupo, Cortez III Service Corporation, 21000 Brookpark Road, Cleveland, Ohio 44142 (currently

with InDyne, Inc., 21000 Brookpark Rd., Cleveland, Ohio 44142). Responsible person, Philip G. Neudeck, organiza-

tion code 5510, (216) 433-8902.

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13. ABSTRACT (Maximum 200 words)

Complex electronics and sensors are increasingly being relied on to enhance the capabilities and efficiency of modern jet

aircraft. Some of these electronics and sensors monitor and control vital engine components and aerosurfaces that operate

at high temperatures above 300 °C. However, since today's silicon-based electronics technology cannot function at such

high temperatures, these electronics must reside in environmentally controlled areas. This necessitates either the use of

long wire runs between sheltered electronics and hot-area sensors and controls, or the fuel cooling of electronics and

sensors located in high-temperature areas. Both of these low-temperature-electronics approaches suffer from serious

drawbacks in terms of increased weight, decreased fuel efficiency, and reduction of aircraft reliability. A family of high-

temperature electronics and sensors that could function in hot areas would enable substantial aircraft performance gains.

Especially since, in the future, some turbine-engine electronics may need to function at temperatures as high as 6130°C.

This paper reports the fabrication and demonstration of the first semiconductor digital logic gates ever to function at

600 °C. Key obstacles blocking the realization of useful 600 °C turbine engine integrated sensor and control electronics

are outlined.

14. SUBJECT TERMS

Silicon carbide; Field effect transistors; JFET; Transistor circuits

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